1. Field of the Invention
This invention relates to a synchronization detection system, a block address generation system and a memory write signal generation system used for recording and reproducing serial digital data.
2. Description of the Prior Art
Among the techniques of serial digital data recording and reproduction used in extensive fields, a recent application is a digital audio tape recorder (DAT). In a rotary-head digital audio tape recorder (R-DAT), for example, a recording signal is formatted in a constant block period Bt as shown in FIG. 4, in which serial digital data D.sub.0, D.sub.1, . . . , D.sub.n are preceded by a synchronizing signal (SYNC) with a specific code pattern, a record identification code (ID), a block address code (BA), and an error detection code (EDC) for the ID and BA. Each code is formed of eight bits, and is called "symbol".
In the following description, the data of the identification code (ID) indicative of the content of recorded data, etc. is denoted by the symbol W.sub.1, the data of the address code BA is denoted by the symbol W.sub.2, and the data of the error detection code EDC is denoted by the symbol P.
The reproducing section has a sync generator providing the same code pattern as that of the recording section, and it compares the reproduced serial digital data with the sync pattern sequentially so as to decide a reproduced signal, when it coincides with the sync pattern, to be a sync signal so that it is used as a reference signal for the successive signal processing. This is the prevalent technique of serial digital data recording and reproduction.
The R-DAT employs a modulation system called "8-10 modulation" with its sync signal (SYNC) having a special pattern which does not appear in data normally, so that the accuracy of sync signal detection is appreciably high. However, in a case where a modulation system having a special sync pattern cannot be used by some reason, for example, because of the band limitation of the recording signals such as when recording both an analog video signal and a digital audio signal, it becomes inevitable to use a code pattern contained in data as a sync signal. In this case, false sync signals other than the valid sync signal will appear with high probability, and normal signal processing will be difficult. Although this problem may be solved by increasing the word length of the sync signal (SYNC), it will result disadvantageously in an increased recording frequency or a degraded signal transmission rate.
A conventional breakthrough technique for ensuring the sync signal detection without an increased word length of the sync signal is, in addition to the use of a first sync signal detection circuit, to detect predetermined regularity in the contents of two consecutive block address codes BA to utilize it as a second sync signal so that a final sync signal is obtained from a logical product of both the first and second sync signals, as disclosed, for example, in Japanese Patent Unexamined Publication No. 60-137150. The block address code BA generally uses a series of binary numbers increasing continuously from zero, and the detection of a predetermined difference in the value between two consecutive address codes ensures the sync signal detection.
However, since the above arrangement utilizes the regularity of two consecutive address codes, it fails to implement the ensured and prompt sync signal detection in such a case where one address code is dropped for example, at the time immediately after the start or the recovery from a code error which has occurred in data reproduction, because it becomes difficult to detect any regularity present in address data values in such a case.
FIG. 5 is a block diagram showing a conventional memory control apparatus. In the reproducing operation, serial digital data is inputted through an input terminal 2, and a sync signal detecting circuit 3 detects the sync signal and produces signals which are in phase with the sync signal. The serial digital data is also applied to a block address latch circuit 4, in which the address code BA is latched in response to a latch pulse supplied from the sync signal detecting circuit 3. The serial digital data is further fed to a parity check circuit 5, in which a positive parity check or a negative parity check is made in accordance with the following equation for the code structure shown in FIG. 4, for example. EQU P=W.sub.1 .sym.W.sub.2 or P=W.sub.1 .sym.W.sub.2
where symbol .sym. represents an exclusive-OR operation.
The sync signal detecting circuit 3 applies one output thereof to a clock terminal of a block address counter circuit 6, which further receives at its reset terminal rotary head switching pulses (the signal S.sub.1 shown in FIG. 2) indicative of the rotational position of the rotary head (not shown) which are supplied through an input terminal 1. The block address counter circuit 6 has its contents cleared at the edge of a head switching pulse and counts the sync signal until it is cleared by a next head switching pulse. This operation is repeated. In FIGS. 1 and 5, numerals indicative of respective short slanting lines crossing the connection lines show bit numbers of digital signals sent through the connection lines, respectively. The block address counter circuit 6 and the block address latch circuit 4 apply their outputs (8 bits) to a block address anticoincidence circuit 8, which decides whether both block address values coincide with each other. The outputs of the block address anticoincidence circuit 8 and the parity check circuit 5 are applied to an AND gate 7, which outputs a pulse when the parity check result is correct and at the same time the block address values do not coincide with each other, and the output pulse is applied to the load terminal L of the block address counter circuit 6, and the 8-bit output of the block address latch circuit 4 is applied to the data terminal D of the block address counter circuit 6 so that the address value of the block address latch circuit 4 is loaded in the block address counter circuit 6. The block address counter circuit 6 produces an 8-bit output, which is outputted through an output terminal 9, and it forms a part of an address signal value for storing the reproduced digital data in a RAM (Randome Access Memory).
Furthermore, the sync signal detecting circuit 3 and the block address counter circuit 6 supply their outputs to a write signal generating circuit 10, which provides an output through an output terminal 11, and it is used as a write signal for storing the reproduced digital data in the RAM.
Hereupon, in a magnetic recording and reproducing apparatus for recording and reproducing a video signal on a magnetic tape by using a rotary head, when recording and reproducing an audio signal in the form of a digital signal, an analog audio signal is digitized at a sampling frequency f.sub.s of 48 kHz, for example, so that a frequency ratio of the sampling frequency f.sub.s of 48 KHz to the field frequency f.sub.v of the video signal of 59.94 Hz in the NTSC system becomes 800.8. The number of data in one field is divided into two kinds, that is, a greater number and a smaller number (e.g., 792 and 810), and supplementary dummy data is added to the field containing a small number of data (792 data in one field) to effect recording. Since the MSB of the address code BA in FIG. 4 is used to record the information indicative of the presence or absence of the supplementary dummy data, the block address value is recorded in 7 bits. For example, when the number of blocks in one field is 135, the lower-order 7 bits of the block address code W.sub.2 include the o-address (0000000) to 127-address (1111111). Then, the next 128-address is indicated by (0000000), and the last 134-address is indicated by 6(=134-128 )-address (0000110). The block addresses are recorded in a magnetic tape with these bit indications.
However, in digitally recording an audio signal in synchronism with a video signal as mentioned above, the 8-bit block address value for the reproduction cannot be produced directly from the recording block address value, since the recording block address is recorded in 7 bits on the magnetic tape.